VLSI TECHNOLOGY1

11.Bipolar IC Manufacturing Process

In this post, we shall discuss, the fabrication of a standard, junction- isolated bipolar IC.  Of course, many devices can be formed at a time over the surface of the water if appropriate patterns are provided. We shall show only one device, that is, a bipolar transistor as an example. The major steps in the IC bipolar process are listed in the diagram below.

Bipolar IC Fabrication Steps

The starting material is a p-type single crystal silicon wafer having 5 to 20 ohm-cm resistivity and thickness of approximately several hundred micrometers. The diameter can be 50, 75, 100, 125, or 150 mm. The most standard size is 100 mm or about 4 inches

1. A thin layer of SiO₂ is formed on all surfaces of a p-type silicon wafer by exposing it to oxygen or water vapour in an electric furnace. The first masking step defines the area for n⁺ buried layers, (also called sub-collector). The function of this layer is to reduce the collector resistance of the transistor. The SiO­₂ is removed in these areas by chemical etching. Thermal diffusion or ion implantation forms the desired heavily doped n-type, that is, n⁺ buried layer region. The resulting structure is shown in the figure below.
2. The SiO₂ masking layer is removed, exposing the entire silicon wafer surface. By epitaxial deposition, an n-type layer is grown, over the entire surface. It is n-type single-crystal silicon 2 to 5 micro meter thick with its resistivity in the range of 0.1 to 1 ohm-cm. During the epitaxial process, the n-type dopant previously introduced in the buried layer areas diffuses in all directions. This is shown in the figure below.
3. The wafer with the epitaxial layer is then oxidized at an elevated temperature in an H₂O ambient. This forms a layer of SiO₂, approximately 0.5 micro meters thick over the entire surface of silicon. A second masking step defines a border completely enclosing n-type islands of silicon that are to be electrically isolated collectors of transistors. P-type diffusion into the border areas is continued until the entire epitaxial layer has been penetrated, as shown in the figure below. Thus, islands of n-type silicon are bounded on all sides by p-type Si. Isolation is achieved by applying voltages such that this p-n junction is always reverse- biased. The p-type diffusion uses boron as impurity. A new layer of thermal oxide is grown over the isolation areas.
4. The third masking step defines base regions of n-p-n transistors. Patterns of resistors are formed simultaneously in separate isolated n-type regions. Boron is again diffused (but this time not as deeply) or implanted to forms bases and resistors. The n-type collector is converted to p-type when the density of p-type impurities exceeds that of n-type impurities. The resulting structure is shown in figure below.
5. The fourth photolithographic step defines n-type transistor emitters and n-type regions for low resistance contacts to collector regions, as in the figure below. Again conversion of p-type base to n-type requires impurity compensation.
6. An oxide is again thermally grown over the entire wafer and via photolithography, (5^th mask) those regions where contact is to be made to the silicon are defined. Metal (AI) is then deposited by vacuum evaporation. The photolithographic process (6^th mask) is then used to define the appropriate metallization inter-connection pattern, and the remaining metal is removed. The figure below shows the contact areas (defined by 5^th mask) to collector, base, and emitter. The 6^thmasking step is not shown in figure.

Bipolar IC Manufacture Steps

At this point, the ICs are in finished state. However before finished form, a protective passivating layer using glass is deposited over the entire wafer. This is known as die passivation or scratch protection, or glassivation. This protects the surface of the wafer from contamination. Glassivation is done using chemical vapour deposition. This added step paysoff in protection before and after packaging, in higher yields and in better reliability.

A final masking step removes the above insulating layer over the pads where contacts will be made. Now the IC chip undergoes a probe test. This is necessary because there are many faulty chips after such highly complicated fabrication steps. The probe test is automatically carried out by contacting the pads of every chip with microelectrode probes. Registration of each chip with respect to the probes is done automatically by final mechanical adjustment.

The chip is then tested using a set of test vectors, which consist of a sequence of input voltages, stimuli (to chip input pads) and expected output voltage responses (from chip output pads) that have been previously generated by the design engineer. If the chip passes all test vectors, namely all outputs provide the correct results for all input stimuli then the probes are automatically stepped to the next chip position and all test vectors are applied to that chip. This process is repeated until all chips have been tested. Chips that failed to pass all test vectors are marked with an ink dot. Due to computer controlled operation of wafer probe equipment, upto 16000 test vectors are tested for each chip of a wafer in some minutes.

Faulty chips will be thrown away later. Now, the entire wafer is broken into individual chips. This is discussed below.

Chip Separation

The entire wafer is divided up into individual chips by “scribe-and-break” operation using any one of the following ways.

• Diamond-tipped scribe
• High-intensity laser beam (laser scribing), or
• High-speed circular saw

Since this process is similar to glass culling it is called scribing and breaking. In the diamond-tipped scribe method, the grooves are very shallow. In laser scribing method, the grooves are somewhat deeper, and may extend more than halfway through the wafer. In the high-speed circular saw method, the wafer will have a pattern of orthogonally oriented “scribing streets” which are kept clear of oxide and metal and are aligned along certain crystallographic directions to promote the easy and smooth cleavage of the wafer.

A popular process for chip separation is to use a wafer saw to cut entirely through the wafer. The wafer is mounted on adhesive-coated tape prior to the sawing operation so that after sawing the chips will remain in matrix form for convenience in further operations.

Faulty chips are identified using probe test mentioned above. Hence, only good chips are mounted in containers. The chips are bonded to either metal headers or ceramic substrate. The metal headers are usually gold-plated Kover. Kovar is an iron-nickel-cobalt alloy whose thermal expansion coefficient is a close match to that of silicon. The headers axe heated to temperatures in the range of 400 to 420°C in an inert-gas atmosphere (N₂ or a mixture of about 90% N₂ and 10% H₂). The chips are then bonded to the headers by means of the formation of a gold-silicon alloy that results in a good mechanical bond and a low-resistance electrical contact. This contact will be the substrate of the IC chip. The same process is used for discrete components, such as transistor. In that case the contact will be the collector of the transistor.

Lead Bonding and Encapsulation

Connecting the pads (metallised contact areas) to the terminal (that is, pins) of container with gold (or aluminium) wires is referred to as bonding. For this purpose small-diameter (20 to 40 micro meters) gold wires are used. Aluminium wire is used especially for high-current power devices, where large-diameter round or flat ribbon leads may be used. Take a look at the figure below.

Lead Bonding

The IC chip is now encapsulated in a metal, ceramic or plastic package. The plastic package is the lowest in cost, but the metal and ceramic package offer the advantage of providing a hermetic seal and a higher operating temperature range.

Sometimes chips are mounted on ceramic sheets without containers. IC prepared in this way is called IC modules. Each IC package is finally tested with its external terminals by feeding electric signals to its input pins and analyzing those at its output pins by a computer. This is a package test.

It should be noted that the fabrication process, discussed above, treats simultaneously a number of wafers, each of which has tens to several hundreds of chips. In 1985, the standard IC utilized 100 mm wafer such as that shown in the figure shown below. The current trend is of 15 cm wafer and 20 cm technology. The wafer thickness, about 0.2 to 0.3 mm, provides the chip with sufficient mechanical rigidity. Each wafer may have 100 to 8000 rectangular chips having side 1 to 10 mm. If we process, twenty-five (say) 10-cm wafers in a single batch production, 200,000 ICs are manufactured at a time. If the average component count per IC were only 800, a batch would contain more, than 100 million components. If the yield, that is, the percentage of fault free chips, is 10% (say) 20,000 good chips are mass produced in a single batch of production. This shows a significant advantage of IC technology.

Encapsulation

A variety of IC packages are available. The most commonly used are dual in-line pack (DIP), flat pack, leadless chip carriers (LCC), and pin grid arrays (PGA). Some of them are discussed in the appendix. The PGA provides a very high pin count in a minimum of area.

It should be emphasized that when circuits are implemented on a single chip and encased into a single package, as above it is called a monolithic integrated circuit. When a package contains more than one chip or a mixture of chips and discrete components (one component per container, i.e., one transistor, per container, for example), all of which are put on a large substrate (such as ceramic substrate), it is called a hybrid integrated circuit.

IC packages are usually placed on a PC board. The pins of IC packages and the holes on the pc board are soldered. Then the pc boards are inserted into mother boards which are placed in cabinets along with backplanes.

Another approach to assemble IC chips is to place chips on a ceramic carrier and then the ceramic carriers on a ceramic mother carrier. The ceramic mother carriers are placed on a pc board. This approach has the advantage of smaller space than IC packages are assembled on a pc board and a lower cost than hybrid ICs.

12.MESFET

The figure below shows a diagram of gallium arsenide (GaAs) MESFET (metal-semiconductor field-effect transistor). MESFET is nothing but a JFET fabricated in GaAs which employs a metal-semiconductor gate region (a Schottky diode). The device operates in essentially the same way as does a junction-gate FET, except that instead of a gate-channel on junction there is a gate-channel Schottky barrier. The depletion region associated with this barrier will control the effective height of the conducting channel and can thereby control the drain-to-source current of the device.

MESFET Structure

The width of this depletion region will increase with increasing gate voltage so that we see again that the gate will be the control electrode and as long as the Schottky barrier is reverse biased, the gate current will be very small.

Electron mobility in GaAs (8500 cm²/v-s) is much higher than that of silicon and allows MESFET operation at frequencies higher than can be achieved with silicon devices. The MESFET also possesses very short channel length. This results in very short channel transit times for electrons. As a result, MESFET can operate well into the range of 1 to 10 gigahertz (GHz). Thus, applications of MESFETs were initially in microwave circuits for high frequency performance.

However, since 1984, high-speed logic circuits employing MESFETs have been produced commercially.

These logic circuits are made compatible with the high-speed bipolar logic family called emitter-coupled logic (EGL).

13.Epitaxial Devices – Characteristics

Junction Characteristics

Before describing the fabrication sequences for ICs, it will be useful to provide insight into the use of epitaxial structures for devices.

A reverse-biased p-n junction can be considered to be a parallel-plate capacitor with the depletion region being the insulator or dielectric as shown in the figure below. The depletion or space-charge region is the region adjacent to the p-n junction that is essentially depleted (or devoid) of all mobile charges (that is, free electrons and holes), so that it acts like an insulator. For almost all diffused p-n junctions the doping on the diffused layer side of the junction will be very much heavier than the doping on the other (substrate) side of the junction, so that most diffused junctions can be considered to be one-sided junctions. The figure (a) corresponds to a general case of p-n junction, while figure (b) corresponds to a one-sided p-n junction. Notice that in the latter case the depletion region is almost entirely on the lightly doped (substrate) side of the junction and extends very little into the diffused layer side.

P-N Junction Depletion Region

For a one sided junction, the breakdown voltage will be a function principal of the doping level on the more lightly doped side of the junction. The equation is given by

V_Z = 2.7 * 10¹² V/N^2/3

The breakdown voltage for planar junctions will be somewhat lower than the values obtained from the above equation, especially at the lighter doping levels, where the breakdown voltage can be very substantially less, this is due to the effect of the junction curvature in the region underneath the edges of the oxide window, which results in an increase in the electric field intensity. At heavier doings, however, the influence of junction curvature on breakdown voltage becomes less. Therefore, for a high breakdown voltage a light doping is required. The junction depth should also not be too small especially for the cases in which very high breakdown voltages, typically more than 100 V, are required.

The bulk series resistance of a p-n junction is due to the finite resistivity of the p-type and n-type regions of the junction, outside the depletion region. For a p-n diffused junction the series resistance due to the p diffused layer will be negligible compared to the resistance due to the n-layer of the junction. Thus for a small value of series resistance a low-resistivity substrate is needed.

Epitaxial Structures

From the above discussion, we can consider the following requirements :

• For low junction capacitance C_j, low doping, that is, lightly doped substrate, is required.
• For high breakdown voltage, low doping, that is, lightly doped substrate, is required.
• For low series resistance, R_s, heavy doping, that is, low resistivity substrate is required.

We see that the series resistance requirement is conflicting with the capacitance and breakdown voltage requirements. The epitaxial structure shown in the figure below, offers a good way of resolving this conflict and simultaneously satisfying the capacitance, breakdown voltage and series resistance requirements. As long as the depletion region remains entirely within the lightly doped epitaxial layer and does not reach the heavily doped n+ substrate, the capacitance and breakdown voltage will be a function only of the epitaxial layer doping and will be independent of the substrate doping.

Planar Epitaxial and Non-Epitaxial Diode

Planar Epitaxial Diode Fabrication Steps

After realizing the purpose of epitaxial layer, we will now summarize the processing steps tor some typical devices, starting with a planar p⁺n/n⁺ diode. Referring to figure (b) given above, the fabrication steps for the epitaxial planar diode are as follows.

• The starting material is n/n⁺ epitaxial wafer with a 0.005-ohm-cm (Sb-doped} substrate and an epitaxial layer of anywhere from 5 to 25 micro meters thick and phosphorus doped to resistivities in the range 5 to 50-ohm-cm.
• An oxide layer about 5000 to 8000A thick is grown.
• Using first photolithography windows are opened in the oxide layer for the P⁺ diffusion.
• A p⁺ diffused layer about 1 to 3 micro meters thick is produced to be the anode region of the diode.
• Using second photolithography anode contact windows are produced.
• Anode contacts are produced using aluminium deposition carried out by metallization process
• Using third photolithography the metallization is patterned for anode contacts.
• The metallization film is sintered or alloyed to form a good mechanical bond to the silicon and to produce a low- resistance, non rectifying ohmic contact. Sintering or alloying is a heat treatment at about 500 to 600°C.
• A back-side metallization is carried out. In this, a thin film of gold is evaporated on to the lapped back side of the wafers. This is for the eutectic die (chip) bonding of the chips to gold-plated headers or substrates at temperatures in the range 400° to 420°C, the gold/silicon eutectic temperature being 370°C.

Planar Epitaxial Transistor

The figure below shows a cross-sectional view of a typical n-p-n planar epitaxial transistor.

Planar Epitaxial Transistor

The processing steps are as follows:

• The starting material is n/n⁺ epitaxial wafer with 0.005 ohm-cm Sb-doped substrate and n-type epitaxial layer of about 6 to 12 micro meters thickness and 0.3 to 3 ohm-cm resistivity.
• An oxide layer of about 5000 to 8000A thickness is grown.
• Using first photolithography, oxide windows arc etched for the base diffusion.
• A two-step deposition-drive in boron diffusion is performed for base region. The junction depth  is about 2 to 3 micro meters. Sheet resistance is of about 200 ohm per square. The drive-in diffusion is performed in an oxidizing ambient so that oxide is regrown in the windows that were produced in the preceding step.
• Using second photolithography, oxide windows are etched for the emitter diffusion.
• A high surface concentration phosphorus diffusion is performed to produce an n⁺ diffused layer emitter region with a junction depth of about 2 to 2.5 micro meters.
• Using third photolithography, oxide windows are etched for emitter and base contacts.
• An aluminium thin film of about 0.5 to 1 micro meter separate thickness is deposited on the front surface of the surface using metallization process.
• Using fourth photolithography, windows are etched for emitter and base contact areas.
• Heat treatment at 500 to 600°C for sintering or alloying the metallization film is carried out.
• A gold thin film is deposited on the back side of the wafers.

Triple Diffused Planar Transistor

Early planar transistors and ICs used only photolithography and diffusion steps in the fabrication process. However, all diffused planar devices had severe limitations compared with discrete devices. In a triple diffused transistor as shown in the figure below, the collector region is formed by an n-type diffusion into the p-type wafer.

Triple Diffused Transistor

The drawbacks of this structure are that the series collector resistance is high and the collector-to-emitter breakdown voltage is low. The former occurs because the impurity concentration in the portion of the collector diffusion below the collector-to-base junction is low giving the region high resistivity. The latter occurs because near the surface of the collector the concentration of impurities is relatively high, resulting in a low breakdown voltage between the collector and base diffusions. Thus the concentration profile provided by the diffused collector is very disadvantageous; what is required is a low impurity concentration at the collector-base junction for high breakdown voltage and a high concentration below the junction for low collector resistance. Such a concentration profile cannot be realized with diffusion alone, and hence the epitaxial growth was adopted. Epitaxial layer is thus a suitable starting material for the fabrication of bipolar transistors.

n-Channel JEET Fabrication Steps

The figure blow shows an n-channel epitaxial JEET structure. The n-type channel is formed by the n-type epitaxial layer region between the p⁺ diffused layer (gate) and the p-type substrate.

n-Channel JFET Structure

The processing sequence for the device follows closely to that of the double-diffused transistor and is summarized below.

• The starting material is n/p epitaxial wafer.
• Thermal oxidation is carried out
• Using first photolithography, windows are opened for p⁺ boron top gate diffusion.
• Boron diffusion for gate region is carried out.
• Using second photolithography windows are opened for n⁺ source and drain diffusion.
• n⁺ phosphorus diffusion is carried out to produce the source and drain regions of the JFET. Using third photolithography, contact windows are opened
• Metallization is carried out.
• Using fourth photolithography metallization patterning for source, drain, and gale contact areas is carried out
• Contact sintering or alloying is done.
• Back-side metallization is carried out.

14.Metallization Process

Metallization is the final step in the wafer processing sequence. Metallization is the process by which the components of IC’s are interconnected by aluminium conductor. This process produces a thin-film metal layer that will serve as the required conductor pattern for the interconnection of the various components on the chip. Another use of metallization is to produce metalized areas called bonding pads around the periphery of the chip to produce metalized areas for the bonding of wire leads from the package to the chip. The bonding wires are typically 25 micro meters diameter gold wires, and the bonding pads are usually made to be around 100×100 micro meters square to accommodate fully the flattened ends of the bonding wires and to allow for some registration errors in the placement of the wires on the pads.

Aluminium

Aluminium (At) is the most commonly used material for the metallization of most IC’s, discrete diodes, and transistors. The film thickness is as about 1 micro meters and conductor widths of about 2 to 25 micro meters are commonly used. The use of aluminium offers the following advantages:

• It has as relatively good conductivity.
• It is easy to deposit thin films of Al by vacuum evaporation.
• It has good adherence to the silicon dioxide surface.
• Aluminium forms good mechanical bonds with silicon by sintering at about 500°C or by alloying at the eutectic temperature of 577°C.
• Aluminium forms low-resistance, non-rectifying (that is, ohmic) contacts with p-type silicon and with heavily doped n-type silicon.
• It can be applied and patterned with a single deposition and etching process.

Aluminium has certain limitations:

1. During packaging operation if temperature goes too high, say 600°C, or if there is overheating due to current surge, Al can fuse and can penetrate through the oxide to the silicon and may cause short circuit in the connection. By providing, adequate process control and testing, such failures can be minimized.
2. The silicon chip is usually mounted in the package by a gold perform or die backing that alloys with the silicon. Gold lead wires have been bonded to the aluminium film bonding pads on the chip, since package lead are usually gold plated. At elevated temperatures, a reaction between the metal of such systems causes formation of intermetallic compounds, known as the purple plague. Purple plague is one of six phases that can occur when gold and aluminium inter-diffuse. Because of dissimilar rate of diffusion of gold and aluminium, voids normally occur in the form of the purple plague. These voids may result in weakened bonds, resistive bonds or catastrophic failure. The problem is generally solved by using aluminium lead wires, or another metal system, in circuits that will be subjected so elevated temperatures. One method is to deposit gold over an under layer of chromium. The chromium acts as a diffusion barrier to the gold and also adheres well to both oxide and gold. Gold has poor adhesion to oxide because it does not oxide itself. However, the chromium-gold process is comparatively expensive, and it has an uncontrollable reaction with silicon during alloying.
3. Aluminium suffers from electromigration which can cause considerable material transport in metals. It occurs because of the enhanced and directional mobility of atoms caused by the direct influence of the electric field and the collision of electrons with atoms, which leads to momentum transfer. In thin-film conductors that carry sufficient current density during device operations, the mode of material transport can occur at much lower temperature (compared to bulk metals) because of the presence of grain boundaries, dislocations and point defects that aid the material transport. Eecctromigration-induced failure is the most important mode of failure in Al lines.

In general the desired properties of the metallization for IC can be listed as follows.

• Low resistivity.
• Easy to form.
• Easy to etch for pattern generation.
• Should be stable in oxidizing ambient , oxidizable.
• Mechanical stability; good adherence, low stress.
• Surface smoothness.
• Stability throughout processing including high temperature sinter, dry or wet oxidation, gettering, phosphorous glass (or any other material) passivation, metallization.
• No reaction with final metal, aluminium.
• Should not contaminate device, wafers, or working apparatus.
• Good device characteristics and life times.
• For window contacts-low contact resistance, minimum junction penetration, low electromigration.

Metallization Application in VLSI

For VLSI, metallization applications can be divided into three groups:

1. Gates for MOSFET
2. Contacts, and
3. Interconnects.

Interconnection metallization interconnects thousands of MOSFETs or bipolar devices using fine-line metal patterns. It is also same as gate metallization for MOSFET. All metallization directly in contact with semiconductor is called contact metallization. Polysilicon film is employed in the form of metallization used for gate and interconnection of MOS devices. Aluminium is used as the contact metal, on devices and as the second-level inter-connection to the outside world. Several new schemes for metallization have been suggested to produce ohmic contacts to a semiconductor. In several cases a multiple-layer structure involving a diffusion barrier has been recommended. Platinum silicide (PtSi) has been used as a Schottky barrier contact and also simply as an ohmic contact for deep junction. Titanium/platinum/gold or titanium/palladium/gold beam lead technology has been successful in providing high-reliability connection to the outside world. The applicability of any metallization scheme in VLSI depends on several requirements. However, the important requirements are the stability of the metallization throughout the IC fabrication process and its reliability during the actual use of the devices.

Ohmic contacts

When a metal is deposited on the semiconductor a good ohmic contact should be formed. This is possible, if the deposition metal does not perturb device characteristics. Also die contact should be stable both electrically and mechanically.

Other important application of metallization is the top-level metal that provides a connection to the outside world. To reduce interconnection resistance and save area on a chip, multilevel metallization, as discussed in this section is also used. Metallization is also used to produce rectifying (Schottky barrier) contacts, guard rings, and diffusion barriers between reacting metallic films.

We have already stated the desired properties of metallization for ICs. None of the metals satisfies all the desired characteristics. Even Al, which has most of the desired properties suffers from a low melting point-limitation and electromigration as discussed above.

Poly-silicon has been used for gate metallization, for MOS devices. Recently, poly-silicon/refractory metal silicide bi-layers have replaced poly-silicon so that lower resistance an be achieved at the gale and interconnection level. By preserving the use of polysilicon as the “metal” in contact with the gate oxide, well known device characteristics and processes have been unaltered. The silicides of molybdenum (MoSi₂), tantalum (TaSi₂) and tungsten (WSi₂) have been used in the production of microprocessors and random-access memories. TiSi₂ and CoSi₂ have been suggested to replace MoSi₂, TaSi₂, and WSi2. Aluminium and refractory metals tungsten and Mo are also being considered for the gate metal.

For contacts, Al has been the preferred metal for VLSI. However, for VLSI applications, several special factors such as shallower junctions, step coverage, electromigration (at higher current densities), and contact resistance can no longer be ignored. Therefore, several possible solutions to the contact problems in VLSI have been considered. These include use of

• Dilute Si-Ai alloy.
• Polysilicon layers between source, drain, or gate and top-level Al.
• Selectively deposited tungsten, that is, deposited by CVD methods so that metal is deposited only on silicon and not on oxide.
• A diffusion barrier layer between silicon and Al, using a silicide, nitride, carbide, or their combination.

Use of self-aligned silicide, such as, PtSi, guarantees extremely good metallurgical contact between silicon and silicide. Silicides are also recommended in processes where shallow junctions and contacts are formed at the same time. The most important requirement of an effective metallization scheme in VLSI is that metal must adhere to the silicon in the windows and to the oxide that defines die window. In this respect, metals such as, Al, Ti, Ta, etc., that form oxides with a heat of formation higher than that of Si0₂ are the best. This is why titanium is the most commonly used adhesion promoter.

Although silicides are used for contact metallization, diffusion barrier is required to protect from interaction with Al which is used as the top metal. Aluminium interacts with most silicides in the temperature range of 200-500 degree Celsius. Hence transition metal nitrides, carbides, and borides are used as a diffusion barrier between silicide (or Si) and Al due to their high chemical stability.

Metallization Processes

Metallisation process can be classified info two types:

1. CVD and
2. Physical Vapour Deposition

To know about CVD click on the link below.

TAKE A LOOK : CHEMICAL VAPOUR DEPOSITION (CVD)

CVD offers three important advantages. They are

• Excellent step coverage
• Large throughput
• Low-temperature processing
• The basic physical vapour deposition methods are
• Evaporation
• Sputtering

Both these methods have three identical steps.

• Converting the condensed phase (generally a solid) into a gaseous or vapour phase.
• Transporting the gaseous phase from the source to the substrate, and
• Condensing the gaseous source on the substrate.

In both methods the substrate is away from the source.

In cases where a compound, such as silicide, nitride, or carbide, is deposited one of the components is as gas and the deposition process is termed reactive evaporation or sputtering.

Deposition Methods

In the evaporation method, which is the simplest, a film is deposited by the condensation of the vapour on the substrate. The substrate is maintained at a lower temperature than that of the vapour. All metals vaporize when heated to sufficiently high temperatures. Several methods of heating are employed to attain these temperatures. For AI deposition, resistive, inductive (RF), electron bombardment [electron-gun] or laser heating can be employed. For refractory metals, electron-gun is very common. Resistive heating provides low throughput. Electron-gun cause radiation damage, but by heat treatment it can be annealed out. This method is advantageous because the evaporations take place at pressure considerably lower than sputtering pressure. This makes the gas entrapment in the negligible. RF heating of the evaporating source could prove to be the best compromise in providing large throughput, clean environment, and minimal levels of radiation damage.

In sputtering deposition method, the target material is bombarded by energetic ions to release some atoms. These atoms are then condensed on the substrate to form a film. Sputtering, unlike evaporation is very well controlled and is generally applicable to all materials metals, alloys, semiconductors and insulators. RF-dc and dc-magnetron sputtering can be used for metal deposition. Alloy-film deposition by sputtering from an alloy target is possible because the composition of the film is locked to the composition of the target. This is true even when there is considerable difference between the sputtering rates of the alloy components. Alloys can also be deposited with excellent control of composition by use of individual component targets. In certain cases, the compounds can be deposited by sputtering the metal in a reactive environment. Thus gases such as methane, ammonia, or nitrogen, and diborane can be used in the sputtering chamber to deposit carbide, nitride, and boride, respectively. This technique is called reactive sputtering. Sputtering is carried out at relatively high pressures (0.1 to 1 pascal or Pa). Because gas ions are the bombarding species, the films usually end up including small amount of gas. The trapped gases cause stress changes. Sputtering is a physical process in which the deposited film is also exposed to ion bombardment. Such ion bombardment causes sputtering damage, which leads to unwanted charges and internal electric fields that affect device proxies. However such damages can be annealed out at relatively low temperatures (<500°C), unless the damage is so severe as to cause an irreversible breakdown of the gate dielectric.

Deposition Apparatus

The metallization is usually done in vacuum chambers. A mechanical pump can reduce the pressure to about 10 to 0.1 Pa. Such pressure may be sufficient for LPCVD. An oil-diffusion pump can bring the pressure down to 10^-5 Pa and with the help of a liquid nitrogen trap as low as 10^-7 Pa. A turbomolecular pump, can bring the pressure down to 10^-8-10^-9 Pa. Such pumps are oil-free and are useful HI molecular-beam epitaxy where oil contamination must be avoided. Besides the pumping system, pressure gauges and controls, residual gas analyzers, temperature sensors, ability to clean the surface of the wafers by backsputtering, contamination control, and gas manifolds, and the use of automation should be evaluated.

As typical high-vacuum evaporation apparatus is shown in the figure below.

Metallization Process

The apparatus consists of a hell jar, a stainless-steel cylindrical vessel closed at the top and sealed at the base by a gasket. Beginning at atmospheric pressure the jar is evacuated by a roughing pump, such as a mechanical rotary-van pump reducing pressure to about 20 Pa or a combination mechanical pump and liquid-nitrogen-cooled molecular pump (reducing pressure lo about 0.5 Pa). At the appropriate pressure, the jar is opened to a high-vacuum pumping system that continues to reduce the pressure. The high-vacuum, pumping system may consist of a liquid nitrogen-cooled trap and an oil-diffusion pump, a trap and a turbomolecular pump, or a trap and a closed-cycle helium refrigerator cryopump. The cryopump acts as a trap and must be regenerated periodically, the turbomolecular and diffusion pumps act  as transfer  pumps, expelling their gas t a forepump. The high vacuum pumping system brings the jar to a low pressure that is tolerable for the deposition process.

All components in the chamber are chemically cleaned and dried. Freedom from sodium contamination is vital when coating MOS devices.

The sputtering system operates with about 1 Pa of argon pressure during film deposition. For sputtering, a throttle valve should be placed between the trap and the high-vacuum pumping system. The argon gas pressure can to be maintained by reducing the effective pumping speed of the high-vacuum pump, while the full pumping speed of the trap for water vapour is utilized. Water vapour and oxygen are detrimental to film quality at background pressures of about 10^-2 Pa.

The use of thickness monitors is common in evaporation and sputtering deposition. This is necessary for controlling the thickness of the film, because thinner film can cause excess current density and excessive thickness can lead to difficulties in etching.

Metallization Patterning

Once the thin-film metallization has been done the film must be patterned to produce the required interconnection and bonding pad configuration. This is done by a photolithographic process of the same type that is used for producing patterns in Si0₂ layers. Aluminium can be etched by a number of acid and base solutions including HCl, H₃PO₄, KOH, and NaOH. The most commonly used aluminium etchant is phosphoric acid with the addition of small amounts of HN0₃ (nitric acid) and acetic acid, to result a moderate etch rate of about 1 micro meter per minute at 50°C. Plasma etching can also be used with aluminium.

Lift-off Process

The lift-off process is an alternative metallization patterning technique. In this process a positive photoresist is spun on the wafer and patterned using the standard photolithographic process. Then the metallization thin film is deposited on top of the remaining photoresist. The wafers are then immersed in suitable solvent such as acetone and at the same time subjected to ultrasonic agitation. This causes swelling and dissolution of the photoresist. As the photoresist comes off it lifts off the metallization on top of it, for the lift-off process to work, the metallization film thickness must generally be somewhat less than the photoresist thickness. This process can, however produce a very fine line-width metallization pattern, even with metallization thickness that are greater than the line width.

Pattering for VLSI Applications

VLSI applications require anisotropic etching techniques for metallization patterning because of the requirements of tight control on metallization dimensions. Therefore dry-etching techniques are most suitable. Reactive-ion etching (RIE) is anisotropic. Hence it is preferred. For RIE, reactive gases such as, Cl₂and CCI₃F are used, hence the name reactive ion etching.

15.Ion Implantation

Ion Implantation is an alternative to a deposition diffusion and is used to produce a shallow surface region of dopant atoms deposited into a silicon wafer. This technology has made significant roads into diffusion technology in several areas. In this process a beam of impurity ions is accelerated to kinetic energies in the range of several tens of kV and is directed to the surface of the silicon. As the impurity atoms enter the crystal, they give up their energy to the lattice in collisions and finally come to rest at some average penetration depth, called the projected range expressed in micro meters. Depending on the impurity and its implantation energy, the range in a given semiconductor may vary from a few hundred angstroms to about 1micro meter. Typical distribution of impurity along the projected range is approximately Gaussian. By performing several implantations at different energies, it is possible to synthesize a desired impurity distribution, for example a uniformly doped region.

Ion Implantation System

A typical ion-implantation system is shown in the figure below.

Ion Implantation System

A gas containing the desired impurity is ionized within the ion source. The ions are generated and repelled from their source in a diverging beam that is focussed before if passes through a mass separator that directs only the ions of the desired species through a narrow aperture. A second lens focuses this resolved beam which then passes through an accelerator that brings the ions to their required energy before they strike the target and become implanted in the exposed areas of the silicon wafers. The accelerating voltages may be from 20 kV to as much as 250 kV. In some ion implanters, the mass separation occurs after the ions are accelerated to high energy. Because the ion beam is small, means are provided for scanning it uniformly across the wafers. For this purpose the focussed ion beam is scanned electrostatically over the surface of the wafer in the target chamber.

Repetitive scanning in a raster pattern provides exceptionally uniform doping of the wafer surface. The target chamber commonly includes automatic wafer handling facilities to speed up the process of implanting many wafers per hour.

Properties of Ion Implantation

The depth of penetration of any particular type of ion will increase with increasing accelerating voltage. The penetration depth will generally be in the range of 0.1 to 1.0 micro meters.

Annealing after Implantation

After the ions have been implanted they are lodged principally in interstitial positions in the silicon crystal structure, and the surface region into which the implantation has taken place will be heavily damaged by the impact of the high-energy ions. The disarray of silicon atoms in the surface region is often to the extent that this region is no longer crystalline in structure, but rather amorphous. To restore this surface region back to a well-ordered crystalline state and to allow the implanted ions to go into substitutional sites in the crystal structure, the wafer must be subjected to an annealing process. The annealing process usually involves the heating of the wafers to some elevated temperature often in the range of 1000°C for a suitable length of time such as 30 minutes.

Laser beam and electron-beam annealing are also employed. In such annealing techniques only the surface region of the wafer is heated and re-crystallized. An ion implantation process is often followed by a conventional-type drive-in diffusion, in which case the annealing process will occur as part of the drive-in diffusion.

Ion implantation is a substantially more expensive process than conventional deposition diffusion, both in terms of the cost of the equipment and the throughput, it does, however, offer following advantages.

Advantages of Ion Implantation

Ion implantation provides much more precise control over the density of dopants deposited into the wafer, and hence the sheet resistance. This is possible because both the accelerating voltage and the ion beam current are electrically controlled outside of the apparatus in which the implants occur. Also since the beam current can be measured accurately during implantation, a precise quantity of impurity can be introduced. Tins control over doping level, along with the uniformity of the implant over the wafer surface, make ion implantation attractive for the IC fabrication, since this causes significant improvement in the quality of an IC.

Due to precise control over doping concentration, it is possible to have very low values of dosage so that very large values of sheet resistance can be obtained. These high sheet resistance values are useful for obtaining large-value resistors for ICs. Very low-dosage, low-energy implantations are also used for the adjustment of the threshold voltage of MOSFET’s and other applications.

An obvious advantage of implantation is that it can be done at relatively low temperatures, this means that doped layers can be implanted without disturbing previously diffused regions. This means a lesser tendency for lateral spreading.

High-Current High-Energy Implantation Machines

The ion-implantation apparatus, discussed above, has limits to energy range. The minimum implantation energy is usually set by the extraction voltage, that is, the voltage causing the ions to move out of the ion source into the mass separator. This voltage (which is typically 20 KeV) cannot be reduced too far without drastically reducing beam current. The maximum implantation energy is set by the design of the high voltage equipment. The only way to circumvent this is to implant multiply-charged ions.

High beam currents are obtained by using multiple extraction electrodes and higher voltages. To get a final beam of suitable energy a combination of acceleration and deceleration modes of operation is used.

The electrostatic scanning is not suitable for high-beam currents, as it disrupts space charge neutrality and leads to beam “blow-up”. Therefore a mechanical scanning system is usually used. In this case, the wafer is scanned past a stationary beam. This method has the added advantage of keeping the same beam angle across the whole wafer, whereas an electrostatic system can vary by ±2° for 100 mm wafers. However, mechanical scanning puts new requirements on the wafer holder.

High-energy implantation, at MeV energies, makes possible several new processing techniques required for VLSI.

High-energy implantation machines however introduce high-voltage breakdown problem. At about 400 KeV of energy electrical breakdown of the air around the high voltage equipment occurs. Hence, above 400 KeV, conventional equipment is used. Also, high energy implants frequently require water stages heated up to 600 degree Celsius, so that self annealing during implantation minimizes damage in the surface layer. Mechanical scanning is used because of the difficulty of electrostatically scanning a high-energy beam.

Problems in VLSI Processing

Now a day’s large diameter wafers are feasible. Large size wafers are necessary for VLSI. This makes the task of uniformly implanting a wafer increasingly difficult. This in turn has effect on sheet resistance. Ion implantation is basically clean process because contaminant ions are separated from the beam before they hit the target. There are still several sources of contamination possible near the end of the beam line, which can result in contaminant dose up to 10 percent of the intended ion dose, for example, metal atoms knocked from chamber walls, water holder, masking aperature and so on.

Annealing, as discussed earlier, is required to repair lattice damage and put dopant atoms on substitutional site where they will be electrically active. The success of annealing is often measured in terms of the fraction of the dopant that is electrically active, as found experimentally using a Hall Effect technique. For VLSI, the challenge in annealing is not simply to repair damage and activate dopant, but to do so while minimizing diffusion so that shallow implants remain shallow. This has motivated much work in rapid thermal annealing (RTA), where annealing times are on the order of seconds. RTA uses tungsten-halogen lamps or graphite resistive strips to heat the wafer from one or both sides as against conventional furnace annealing where times or on the order of minutes.

Modern device structures, such as the lightly-doped drains (LDD) for MOSFET, require precise control of dopant distribution vertically and lateral on a very fine scale.  For VLSI CMOS structure, we need to form shallow n and layers with implantation energies within the reach of standard machines. As stated earlier, the ion velocity, perpendicular to the surface, determines the projected range of an implanted ion distribution. If the water is tilted at a large angle to the ion beam then the effective ion energy is greatly reduced tilted ion beams, thus, make it possible to achieve extremely shallow dopant distributions using comparatively high implantation energies. We can circumvent the problem of implanting a shallow layer in silicon completely if instead we implant entirely into a surface layer and then diffuse the dopant into the substrate. This is most often done when the surface film is to be used as a conductor making contact to the substrate. Diffusion results in steep dopant profiles without damage to the silicon lattice. Dopant diffusion in silicides and polysilicon is generally much faster than in single-crystal silicon, so the implanted atoms soon become uniformly distributed in the film.

Importance of Ion Implantation for VLSI Technology

Ion implantation is a very popular process for VLSI because it provides more precise control of dopants (as compared to diffusion). With the reduction of device sizes to the submicron range, the electrical activation of ion-implanted species relies on a rapid thermal annealing technique, resulting in as little movement of impurity atoms as possible. Thus, diffusion process has become less important than methods for introducing impurity atoms into silicon for forming very shallow junctions, an important feature of VLSI circuits. Ion, implantation permits introduction of the dopant in silicon that is controllable, reproducible and free from undesirable side effects. Over the past few years, ion implantation has been developed into a very powerful tool for IC fabrication. Its attributes of controllability and reproducibility make it a very versatile tool, able to follow the trends to finer-scale devices. Ion implantation continues to find new applications in VLS technologies.

16.Diffusion of Impurities for IC Fabrication

The process of junction formation, that is transition from p to n type or vice versa, is typically accomplished by the process of diffusing the appropriate dopant impurities in a high temperature furnace. Impurity atoms are introduced onto the surface of a silicon wafer and diffuse into the lattice because of their tendency to move from regions of high to low concentration. Diffusion of impurity atoms into silicon crystal takes place only at elevated temperature, typically 900 to 1100°C.

Although these are rather high temperatures, they are still well below the melting point of silicon, which is at 1420°C. The rate at which the various impurities diffuse into silicon will be of the order of 1 micro meter per hour at a temperature range stated above, and the penetration depth that are involved in most diffusion processes will be of the order of 0.3 to 30 micro meter. At room temperature the diffusion process will be so extremely slow such that the impurities can be considered to be essentially frozen in place.

A method of p-n junction formation which was popular in the early days is the grown junction technique. In this method the dopant is abruptly changed in the melt during the process of crystal growth. A convenient technique for making p-n junction is the alloying of a metal containing doping atoms on a semiconductor with the opposite type of dopant. This is called the alloyed junction technique. The p-n junction using epitaxial growth is widely used in ICs. An epitaxial grown junction is a sharp junction. In terms of volume of production, the most common technique for forming p-n junctions is the impurity diffusion process. This produces diffused junction. Along with diffusion process the use of selective masking to control junction geometry, makes possible the wide variety of devices available in the form of IC’s. Selective diffusion is an important technique in its controllability, accuracy and versatility.

Nature of Impurity Diffusion

The diffusion of impurities into a solid is basically the same type of process as occurs when excess carriers are created non-uniformly in a semiconductor which cause carrier gradient. In each case, the diffusion is a result of random motion, and particles diffuse in the direction of decreasing concentration gradient The random motion of impurity atoms in a solid is, of course, rather limited unless the temperature is high. Thus diffusion of doping impurities into silicon is accomplished at high temperature as stated above.

There are mainly two types of physical mechanisms by which the impurities can diffuse into the lattice. They are

1. Substitutional Diffusion

At high temperature many atoms in the semiconductor move out of their lattice site, leaving vacancies into which impurity atoms can move. The impurities, thus, diffuse by this type of vacancy motion and occupy lattice position in the crystal after it is cooled. Thus, substitutional diffusion takes place by replacing the silicon atoms of parent crystal by impurity atom. In other words, impurity atoms diffuse by moving from a lattice site to a neighbouring one by substituting for a silicon atom which has vacated a usually occupied site as shown in the figure below.

Substitutional Diffusion By Dopant Impurities

Substitutional diffusion mechanism is applicable to the most common diffusants, such as boron, phosphorus, and arsenic. These dopants atoms are too big to fit into the interstices or voids, so the only way they can enter the silicon crystal is to substitute for a Si atom.

In order for such an impurity atom to move to a neighbouring vacant site, it has to overcome energy barrier which is due to the breaking of covalent bonds. The probability of its having enough thermal energy to do this is proportional to an exponential function of temperature. Also, whether it is able to move is also dependent on the availability of a vacant neighbouring site and since an adjacent site is vacated by a Si atom due to thermal fluctuation of the lattice, the probability of such an event is again an exponent of temperature.

The jump rate of impurity atoms at ordinary temperatures is very slow, for example about 1 jump per 10⁵⁰years at room temperature! However, the diffusion rate can be speeded up by an increase in temperature. At a temperature of the order 1000 degree Celsius, substitutional diffusion of impurities is practically realized in sensible time scales.

2. Interstitial Diffusion

In such, diffusion type, the impurity atom does not replace the silicon atom, but instead moves into the interstitial voids in the lattice. The main types of impurities diffusing by such mechanism are Gold, copper, and nickel. Gold, particularly, is introduced into silicon to reduce carrier life time and hence useful to increase speed at digital IC’s.

Because of the large size of such metal atoms, they do not usually substitute in the silicon lattice. To understand interstitial diffusion, let us consider a unit cell of the diamond lattice of the silicon which has five interstitial voids. Each of the voids is big enough to contain an impurity atom. An impurity atom located in one such void can move to a neighbouring void, as shown in the figure below.

Interstitial Diffusion of Impurity Atom

In doing so it again has to surmount a potential barrier due to the lattice, this time, most neighbouring interstitial sites are vacant so the frequency of movement is reduced. Again, the diffusion rate due to this process is very slow at room temperature but becomes practically acceptable at normal operating temperature of around 1000 degree Celsius. It will be noticed that the diffusion rate due to interstitial movement is much greater than for substitutional movement. This is possible because interstitial diffusants can fit in the voids between silicon atoms. For example, lithium acts as a donor impurity in silicon, it is not normally used because it will still move around even at temperatures near room temperature, and thus will not be frozen in place. This is true of most other interstitial diffusions, so long-term device stability cannot be assured with this type of impurity.

Fick’s Laws of Diffusion

The diffusion rate of impurities into semiconductor lattice depends on the following

• Mechanism of diffusion
• Temperature
• Physical properties of impurity
• The properties of the lattice environment
• The concentration gradient of impurities
• The geometry of the parent semiconductor

The behaviour of diffusion particles is governed by Fick’s Law, which when solved for appropriate boundary conditions, gives rise to various dopant distributions, called profiles which are approximated during actual diffusion processes.

In 1855, Fick drew analogy between material transfer in a solution and heat transfer by conduction. Fick assumed that in a dilute liquid or gaseous solution, in the absence of convection, the transfer of solute atoms per unit area in a one-dimensional flow can be described by the following equation

F = -D ∂N(x,t)/∂x = -∂F(x,t)/∂x

where F is the rate of transfer of solute atoms per unit area of the diffusion flux density (atoms/cm²-sec). N is the concentration of solute atoms (number of atoms per unit volume/cm³), and x is the direction of solute flow. (Here N is assumed to be a function of x and t only), t is the diffusion time, and D is the diffusion constant (also referred to as diffusion coefficient or diffusivity) and has units of cm²/sec.

The above equation is called Fick’s First law of diffusion and states that the local rate of transfer (local diffusion rate) of solute per unit area per unit time is proportional to the concentration gradient of the solute, and defines the proportionality constant as the diffusion constant of the solute. The negative sign appears due to opposite direction of matter flow and concentration gradient. That is, the matter flows in the direction of decreasing solute concentration.

Fick’s first law is applicable to dopant impurities used in silicon. In general the dopant impurities are not charged, nor do they move in an electric field, so the usual drift mobility term (as applied to electrons and holes under the influence of electric field) associated with the above equation can be omitted. In this equation N is in general function of x, y, z and t.

The change of solute concentration with time must be the same as the local decrease of the diffusion flux, in the absence of a source or a sink. This follows from the law of conservation of matter. Therefore we can write down the following equation

∂N(x,t)/∂t = -∂F(x,t)/∂x

Substituting the above equation to ‘F’. We get

∂N(x,t)/∂t = ∂/∂x[D*∂N(x,t)/∂x]

When the concentration of the solute is low, the diffusion constant at a given temperature can be considered as a constant.

Thus the equation becomes,

∂N(x,t)/∂t = D[∂²N(x,t)/∂x²]

This is Ficks second law of distribution.

Diffusion Profiles

Depending on boundary equations the Ficks Law has two types of solutions. These solutions provide two types of impurity distribution namely constant source distribution following complimentary error function (erfc) and limited source distribution following Gaussian distribution function.

Constant Source (erfc) Distribution

In this impurity distribution, the impurity concentration at the semiconductor surface is maintained at a constant level throughout the diffusion cycle. That is,

N (o,t) = N_S = Constant

The solution to the diffusion equation which is applicable in this situation is most easily obtained by first considering diffusion inside a material in which the initial concentration changes in same plane as x=0, from N_S to 0. Thus the equation can be written as

N (o,t) = N_S = Constant and N(x,t) = 0

Shown below is a graph of the complementary error function for a range of values of its argument. The change in concentration of impurities with time, as described by the equation is also shown in the figure below. The surface concentration is always held at N_S, falling to some lower value away from the surface. If a sufficiently long time is allowed to elapse, it is possible for the entire slice to acquire a dopant level of N_S per m³.

Complimentary Error Function

If the diffused impurity type is different from the resistivity type of the substrate material, a junction is formed at the points where the diffused impurity concentration is equal to the background concentration already present in the substrate.

In the fabrication of monolithic IC’s, constant source diffusion is commonly used for the isolation and the emitter diffusion because it maintains a high surface concentration by a continuous introduction of dopant.

There is an upper limit to the concentration of any impurity that can be accommodated at the semiconductor wafer at some temperature. This maximum concentration which determines the surface concentration in constant source diffusion is called the solid solubility of the impurity.

Limited Source Diffusion or Gaussian Diffusion

Here a predetermined amount of impurity is introduced into the crystal unlike constant source diffusion. The diffusion takes place in two steps.

1. Predeposition Step – In this step a fixed number of impurity atoms are deposited on the silicon wafer during s short time.

2. Drive-in step – Here the impurity source is turned off and the amounts of impurities already deposited during the first step are allowed to diffuse into silicon water.

The essential difference between the two types of diffusion techniques is that the surface concentration is held constant for error function diffusion. It decays with time for the Gaussian type owing to a fixed available doping concentration Q. For the case of modelling the depletion layer of a p-n junction, the erfc is modelled as a step junction and the Gaussian as a linear graded junction. In the case of the erfc, the surface concentration is constant, typically the maximum solute concentration at that temperature or solid solubility limit.

Parameters which affect diffusion profile

• Solid Solubility – In deciding which of the availability impurities can be used, it is essential to know if the number of atoms per unit volume required by the specific profile is less than the diffusant solid solubility.

• Diffusion temperature – Higher temperatures give more thermal energy and thus higher velocities, to the diffused impurities. It is found that the diffusion coefficient critically depends upon temperature. Therefore, the temperature profile of diffusion furnace must have higher tolerance of temperature variation over its entire area.

• Diffusion time – Increases of diffusion time, t, or diffusion coefficient D  have similar effects on junction depth as can be seen from the equations of limited and constant source diffusions. For Gaussian distribution, the net concentration will decrease due to impurity compensation, and can approach zero with increasing diffusion tunes. For constant source diffusion, the net Impurity concentration on the diffused side of the p-n junction shows a steady increase with time.

• Surface cleanliness and defects in silicon crystal - The silicon surface must be prevented against contaminants during diffusion which may interfere seriously with the uniformity of the diffusion profile. The crystal defects such as dislocation or stacking faults may produce localized impurity concentration. This results in the degradation of junction characteristics. Hence silicon crystal must be highly perfect.

Basic Properties of the Diffusion Process

Following properties could be considered for designing and laying out ICs.

• When calculating the total effective diffusion time for given impurity profile, one must consider the effects of subsequent diffusion cycles.
• The erfc and Gaussian functions show that the diffusion profiles are functions of (x/ √Dt). Hence, for a given surface and background concentration, the junction depth x1 and x2 associated with the two separate diffusions having different times and temperature
• Lateral Diffusion Effects – The diffusions proceed sideways from a diffusion window as well as downward. In both types of distribution function, the side diffusion is about 75 to 80 per cent of the vertical diffusion.

Dopants and their Characteristics

The dopants selection affects IC characteristics. Boron and phosphorus are the basic dopants of most ICs. Arsenic and antimony, which are highly soluble in silicon and diffuse slowly, are used before epitaxial processing or as a second diffusion. Gold and silver diffuse rapidly. They act as recombination centres and thus reduce carrier life time.

Boron is almost an exclusive choice as an acceptor impurity in silicon since other p-type impurities have limitations as follows :

Gallium has relatively large diffusion coefficient in Si0₂, and the usual oxide window-opening technique for locating diffusion would be inoperative, Indium is of little interest because of its high acceptor level of 0.16 eV, compared with 0.01 eV for boron, which indicates that not all such acceptors would be ionized at room temperature to produce a hole. Aluminium reacts strongly with any oxygen that is present in the silicon lattice.

The choice of a particular n-type dopant is not so limited as for p-type materials. The n-type impurities, such as phosphorus, antimony and arsenic, can be used at different stages of IC processing. The diffusion constant of phosphorus is much greater than for Sb and As, being comparable to that for boron, which leads to economies resulting from shorter diffusion times.

Dopants in VLSI Technology

The common dopants in VLSI circuit fabrication are boron, phosphorus. and arsenic. Phosphorus is useful not only as an emitter and base dopant, but also far gettering fast-diffusing metallic contaminants, such as Cu and An, which cause junction leakage current problems. Thus, phosphorus is indispensable in VLSI technology. However, n-p-n transistors made with arsenic-diffused emitters have better low-current gain characteristics and better control of narrow base widths than those made with phosphorus-diffused emitters. Therefore, in V LSI, the use of phosphorus as an active dopant in small, shallow junctions and low-temperature processing will be limited to its use as the base dopant of p-n-p device and as a gettering agent. Arsenic is the most frequently used dopant for the source and drain regions in n-channel MOSFETs.

Diffusion Systems

Impurities are diffused from their compound sources as mentioned above. The method impurity delivery to wafer is determined by the nature of impurity source; Two-step diffusion is widely technique. Using this technique, the impurity concentration and profiles can be carefully controlled. The type of impurity distribution (erfc or Gaussian) is determined by the choice of operating conditions.

The two-step diffusion consists of a deposition step and a drive-in step. In the former step a constant source diffusion is carried out for a short time, usually at a relatively low temperatures, say, 1000°C. In the latter step, the impurity supply is shutoff and the existing dopant is allowed to diffuse into the body of the semiconductor, which is now held at a different temperature, say 1200°C, in an oxidizing atmosphere. The oxide layer which forms on tire surface of the wafer during this step prevents further impurities from entering, or those already deposited, from diffusing out. The final impurity profile is a function of diffusion condition, such as temperature, time, and diffusion coefficients, for each step.

• Diffusion Furnace

For the various types of diffusion (and also oxidation) processes a resistance-heated tube furnace is usually used. A tube furnace has a long (about 2 to 3 meters) hollow opening into which a quartz tube about 100,150 mm in diameter is placed as shown in the figure below.

Diffusion Furnace

The temperature of the furnace is kept about1000°C. The temperature within the quartz furnace tube can be controlled very accurately such that a temperature within 1/2°C of the set-point temperature can be maintained uniformly over a “hot zone” about 1 m in length. This is achieved by three individually controlled adjacent resistance elements. The silicon wafers to be processed are stacked up vertically into slots in a quartz carrier or “boat” and inserted into the furnace lube.

Diffusion Of p-Type Impurity

Boron is an almost exclusive choice as an acceptor impurity in silicon. It has a moderate diffusion coefficient, typically of order I0-16 m2/sec at 1150°C which is convenient for precisely controlled diffusion. It has a solid solubility limit of around 5 x 1026 atoms/m3, so that surface concentration can be widely varied, but most reproducible results are obtained when the concentration is approximately 1024/m3, which is typical for transistor base diffusions.

• Boron Diffusion using B₂H₆ (Diborane) Source

This is a gaseous source for boron. This can be directly introduced into the diffusion furnace. A number of other gases are metered into the furnace. The principal gas flow in the furnace will be nitrogen (N₂) which acts as a relatively inert gas and is used as a carrier gas to be a dilutent for the other more reactive gases. The N₂, carrier gas will generally make up some 90 to 99 percent of the total gas flow. A small amount of oxygen and very small amount of a source of boron will make up the rest of the gas flow. This is shown in the figure below. The following reactions will be occurring simultaneously at the surface of the silicon wafers:

Si + 0₂ = SiO₂ (silica glass)

2B₂H₆ + 30₂ = B₂O₃ (boron glass) + 6H₂

This process is the chemical vapour deposition (CVD) of a glassy layer on (lie silicon surface which is a mixture of silica glass (Si0₂) and boron glass (B₂0₃) is called borosilica glass (BSG). The BSG glassy layer, shown in the figure below, is a viscous liquid at the diffusion temperatures and the boron atoms can move around relatively easily.

Diffusion Of Dopants

Furthermore, the boron concentration in the BSG is such that the silicon surface will be saturated with boron at the solid solubility limit throughout the time of the diffusion process as long as BSG remains present. This is constant source (erfc) diffusion. It is often called deposition diffusion. This diffusion step is referred as pre-deposition step in which the dopant atoms deposit into the surface regions (say 0.3 micro meters depth) of the silicon wafers. The BSG is preferable because it protects the silicon atoms from pitting or evaporating and acts as a “getter” for undesirable impurities in the silicon. It is etched off before next diffusion as discussed below.

The pre-deposition step, is followed by a second diffusion process in which the external dopant source (BSG) is removed such that no additional dopants cuter the silicon. During this diffusion process the dopants that are already in the silicon move further in and are thus redistributed. The junction depth increases, and at the same time the surface concentration decreases. This type of diffusion is called drive-in, or redistribution, or limited-source (Gaussian diffusion).

• Boron Diffusion using BBr₃i (Boron Tribromide) Source

This is a liquid source of boron. In this case a controlled flow of carrier gas (N₂,) is bubbled through boron tribromide, as shown in the figure below, which with oxygen again produces boron trioxide (BSG) at the surface of the wafers as per following reaction :

4BBr₃ + 30₂ = B20₃ + 2Br₂

Diffusion of n-Type Impurity

For phosphorus diffusion such compounds as PH3 (phosphine) and POCl3 (phosphorus oxychloride) can be used. In the case of a diffusion using PoCI3, the reactions occurring at the silicon wafer surfaces will be:

Si + 02 = SiO2 (silica glass)

4POCl + 30₂ = 2P₂0₅ + 6Cl₂

This will result in the production of a glassy layer on the silicon wafers (hat is a mixture of phosphorus glass and silica glass called phosphorosilica glass (PSG), which is a viscous liquid at the diffusion temperatures. The mobility of the phosphorus atoms in this glassy layer and the phosphorus concentration is such that the phosphorus concentration at the silicon surface will be maintained at the solid solubility limit throughout the time of the diffusion process (similar processes occur with other dopants, such as the case of arsenic, in winch arsenosilica glass is formed on the silicon surface.

The rest of the process for phosphorus diffusion is similar to boron diffusion, that is, after deposition step, drive-in diffusion is carried out.

P₂0₅ is a solid source for phosphorus impurity and can be used in place of POCl₃. However POCl₃ offers certain advantages overP205 such as easier source handling, simple furnace requirements, similar glassware for low and high surface concentrations and better control of impurity density from wafer to wafer and from run to run.

17.Electron-Beam Lithography

Electron-beam lithography provides better resolution then photolithography. This is possible because of small wavelength of the 10-50 KeV electrons. The resolution of electron-beam lithography system is not limited by diffraction, but by electron scattering in the resist and by the various aberrations of the electron optics. The electron-beam exposure system (EBES) machine has proved to be the best photomask pattern generator. However, the pattern writing is in serial form. Therefore, the throughput is much less than for optical systems. In the earlier years of development, electron-beam lithography was employed in the production of low-volume integrated circuits.

Resists

There is a formation of bonds or cross-links between polymer chains when negative resist is exposed to electron beam. However, bond breaking occurs in positive resist when it is exposed. The electron-beam induced cross-links between molecules of negative resist make the polymer less soluble in the developer solution. Resist sensitivity increases with increasing molecular weight. In positive resist the bond breaking process predominates. Thus exposure leads to lower molecular weight and greater solubility.

The polymer molecules in the unexposed resist will have a distribution of length or molecular weight and thus a distribution of sensitivities to radiation.

The narrower the distribution, the higher will be the contrast. High molecular weight and narrow distribution are advantageous.

The resist resolution is limited by swelling of the resist in the developer and electron scattering. Swelling is of more concern for the negative resist and this occurs in all types of lithography, that is, optical, electron, or X-ray. Swelling leads to poor adhesion of resist to the substrate. This problem becomes less severe as resist thickness is reduced.

There is also a fundamental process limitation on resolution. When electrons are incident on a resist or other material, they inter the material and lose energy by scattering, thus producing secondary electrons and X-rays. This limits the resolution to an extent that depends on resist thickness, beam energy, and substrate composition.

For thinner resist layers the resolution is better. Minimum thickness, however, is set by the need to keep defect density low and by resistance to etching as used while device processing. For photomasks where the surface is fiat and only a thin layer of chrome must be etched with a liquid etchant, resist thickness in the range of 0.2 to 0.4 micro meters are used. In case of more severe dry gas plasma etching process employed, thickness of 0.5 micro meters to 2 micro meters are required. One way to overcome this problem is to use a multilayer resist structure in which the thick bottom layer consists of the process-resistant polymer. A three-layer resist structure may be used in which the uppermost layer is used to pattern a thin intermediate layer, such as SiO₂which serves as a mask for etching the thick polymer below. For electron lithography a conducting layer can be substituted for the SiO₂ layer to prevent charge build-up that can lead to beam placement errors.

Multilayer resist structure also alleviates the problem of proximity effect encountered during electron-beam exposure. In this, an exposed pattern element adjacent to another element receives exposure not only from the incident electron beam but also from scattered electrons from the adjacent elements. A two- layer resist structure is also used. In such structure, both the thin upper and the thick lower layer are positive electron resist, but they are developed in different solvents. The thick layer can be overdeveloped to provide the undercut profile that is ideal for lift-off process.

Electron Optics

The first widespread use of electron-beam pattern generators has been in photomask making as discussed in previous section. The EBES machine, as stated earlier, has proved to be the best photomask pattern generator. Scanning electron-beam pattern generators are similar to scanning electron microscopes, from which they are derived. A basic probe-forming electron optical system may consist of two or more magnetic lenses and provisions for scanning the image and blanking the beam on the wafer image plane. Typical image spot sizes are in the range from 0.1 to 2 micro meters. This is for from the diffraction limits. Hence diffraction can be ignored. However, abberations of the final lens and of the deflection system will increase the size of the spot and can change its shape as well.

Electron Projection Printing

Electron projection system provides high resolution over a large field with high throughput. Rather than a small beam writing the pattern in serial fashion, a large beam provides parallel exposure of large area pattern. In a 1:1 projection system parallel electric and magnetic fields image electrons onto the wafer. The mask is of quartz and is patterned with chrome. It is covered with CsI on the side facing the wafer. Photoelectrons are generated on the mask/cathode by backside UV illumination.

The advantages of the projection system are stable mask, good resolution, fast step-repeat exposure with low sensitivity electron resists, large field, and fast alignment. The limitations of the system include proximity effects of electrons and shorter life of cathode.

Electron Proximity Printing

This is a step-repeat system in which a silicon membrane stencil mask containing one chip pattern is shadow printed onto the wafer. The mask cannot accommodate re-entrant geometries. Registration is accomplished by reference to alignment mask on each chip. An advantage of electron proximity printing is its ability to measure and compensate for mask distortions. Proximity effects must be treated by changing the size of pattern elements. The main limitation of the system is the need for two masks for each pattern.

18.Ion-Beam Lithography

Ion-Beam Lithography

Ion-beam lithography, when used to expose resist, provides higher resolution than that possible with an electron-beam because of less scattering. Also, resists are more sensitive to ions than to electrons. A unique feature of ion-beam is that there is the possibility of wafer processing without resists if it is used to implant or sputter selected areas of the wafer. The most important application is repair of photomask, a task for which commercial systems are available.

Ion-lithography employs a scanning focussed-beam or a masked-beam. The problems of ion-optics for scanning ion beams are more severe than for electron optics. The source of ionized material is a gas surrounding a pointed tungsten tip or a liquid metal that flows to the tip from a reservoir. Electrostatic lenses rather than magnetic are used for focussing ion beams. If a magnetic lens were used, the field would have to be much larger than in the electron optics case. Electrostatic optical systems generally have higher aberrations, necessitating small aperature and small scan fields.

Comparison of Various Lithographies

It is expected that photolithography will continue to improve with wavelengths approaching 190 nanometers, the limit for silica. The photo wafer stepper will be the lithography system of choice for many years because of its relative simplicity, convenience, and reasonably high throughput. The practical resolution limit in production application will be 0.5 micro meters or slightly lower. The main limitation to higher photolithographic resolution are

• Optical material
• Small depth of focus
• The difficulty of obtaining diffraction-limited imaging over a large field.

The scanning electron-beam systems are being employed in custom ICs for which high throughput is not needed. The custom ICs require fine definition, good overlay, flexibility, and quick turn around. The main limitation of scanning system is complexity and low throughput. The throughput for scanning system is roughly inversely proportional to the square of the linewidth.

The X-ray lithography with storage ring source and masked ion-beam lithography are the main candidates for high-volume production of advanced circuits with dimensions beyond the optical limit.