VLSI TECHNOLOGY

Labels:

1.Double-Diffused MOS (DMOS)

In this article, the Double-Diffused MOS (DMOS) structure is explained with a diagram. The working of Vertical DMOS Transistor is also explained in detail with its structural analysis and diagram.
To know the basics of DMOS take a look at the following posts.
The figure below shows a double-diffused MOS (DMOS) structure. The channel length, L, is controlled by the junction depth produced by the n+ and p-type diffusions underneath the gate oxide. L is also the lateral distance between the n+ p junction and the p-n substrate junction. The channel length can be made to a smaller distance of about 0.5 micro meters. Thus, this process is similar to the situation with respect to the base width of a double-diffused bipolar transistor. When a fairly large positive voltage is applied to the gate [>VTH], it will cause the inversion of the p-substrate region underneath the gate to n- type , and the n-type surface inversion layer that is produced will act as a conducting channel for the flow of electrons from source to drain.
DMOS Structure
DMOS Structure
From the structure it is known that the n-type substrate is very lightly doped. This will help in making enough space for the expansion of the depletion region between the p-type diffusion region and the n+ drain contact region. Due to this, the breakdown voltage will become higher between the drain and source [BVDS].

Vertical DMOS Structure

The figure below shows a vertical DMOS structure. In this case the drain contact region is the n+ substrate. If the n drain contact regions from the top surface is removed, more parallel-connected channels can be formed. This will naturally increase the transfer conductance and the drain current capability of the device. With a large high-density array of  many gate electrodes on the top surface, vertical DMOS devices with current ratings of up to 10 A are possible.
The double-diffused MOS structure as shown above was one of the earlier successful efforts in the application of short-channel MOSFET technology. The name “DMOS” comes from the smanner of sequence in which the p- doped substrate is first diffused and later followed by highly doped n+ source diffusion. Further developments were made in the DMOS process so that it became one of major power FET technologies. But the first type of DMOS devices were very large in size due to their  lateral structures. Because of this their advantages were soon offset. As a result vertical structures were  designed and developed. There are two principal variations of vertical MOSFET structures. One variation is shown in the figure below. Another type of vertical MOS structure is discussed in the next post. To know more about it, click on the link below.
TAKE A LOOK : V-GROOVE MOS (VMOS)
V-DMOS Transistor
V-DMOS Transistor
As shon in the figure above, most of the high-voltage, high power DMOS structures are constructed with the source and gate located on the top of the chip-and the drain on the underside. VDMOS power FET’s have the power to withstand extremely high voltages with device ratings approaching the kilovolt range. Operationally, there is not much difference between the vertical structure and its planar or lateral equivalent. But VDMOS with smaller chip size have a higher yield. They also have a higher breakdown voltage.

    2.Short Channel MOS Structures

This article discusses the different factors that limit the speed of a MOSFET. The common methods to reduce the parasitics like Scaled MOS (SMOS) and High-performance MOS (HMOS) is explained in detail with their structure and diagram.
There are many factors that limit the speed of a MOSFET. Because of the parasitic capacitances and resistances, the change in the channel current and output voltage  occur slowly. This is due to the fact that when the input voltage at the gate input is changed, the parasitic capacitances must be either charged or discharged through a parasitic resistance. When the parasitics are greater, the charging or discharging become slower. The parasitic capacitances of diffusion regions against the gate and substrate namely, Cgd, Cgs, Cdb and Csb, have sufficient values. These parasitics can be reduced by the self-aligned gate structure.
The parasitics can also be reduced by scaling down of the dimensions. Some common methods are explained below.

1. Scaled MOS (SMOS)

The main purpose of scaling down the dimensions of a MOSFET with a metal gate or a silicon gate is that it will help in increasing the speed of the MOSFET and also reduces the power consumption. When a change in the speed and power consumption occurs the parasitic capacitances will also be reduced. But, for the appropriate working certain adjustments in the parameters must also be made.  In particular, reduction of channel length, that is, the length between drain and source increases the speed because the transit time of the earners to cross the channel is reduced, and the parasitic capacitances are also reduced.
For a MOSFET to work properly, the channel length should nbe minimum. But if it is too short, thats is about 0.2 micro meters, the MOSFET will have certain complex physical phenomenons such as voltage breakdown, and punch through. The punch through causes current flow between source and drain without being controlled by the gate voltage. The minimum channel length in 1976 for depletion mode MOSFET was 6 micro meters which was brought down to 1.5 micro meters in 1982. This has reduced correspondingly the delay of a logic gate using MOS from 4 nano seconds to 0.2 micro seconds. It should be noted that for the sake of convenience, the horizontal length L of the silicon gate in the figure shown below is usually called channel length by the manufacturers because this length appears in a mask. In order to differentiate it from the real channel length L, this could be called a mask channel length. A scaled down n-MOS is usually called high-performance MOS (HMOS), as announced in 1977 by Intel and improved in later years.
Silicon MOS and High Performance MOS
SMOS and HMOS

2. High-Performance MOS (HMOS)

An HMOS device employs a single ion implantation to increase the doping level at the surface region of MOS. This method is employed so as to control the threshold voltage and increase the punch-through voltage. A double implanted HMOS as shown in the second figure above has p1 and p2 regions. The p1 region contains the threshold control implant, and the p2 region contains the punch-through control implant. By the use of these double implants, the HMOS with physically small-channel lengths can be used to minimise the effects occurring due to short channel. As the channel is shortened, departure from long- channel behaviour may occur as a result of a two dimensional potential distribution and high electric fields in the channel region.
The higher transfer conductance, in turn, leads to a larger voltage gain and gain-bandwidth product. Also, the drain current ID at any given gate voltage will be larger, so that the current- handling capability of the device is increased. Indeed, current ratings of up to 10 A are available with some

3.NMOS Fabrication Process

In this article the various steps needed for NMOS Fabrication are explained in detail along with diagrams.
There are a large number and variety of basic fabrication steps used in the production of modern MOS ICs. The same process could be used for the designed of NMOS or PMOS or CMOS devices. The gate material could be either metal or poly-silicon (as described in this article for NMOS device). The most commonly used substrate is bulk silicon or silicon-on-sapphire (SOS). Inorder to avoid the presence of parasitic transistors, variations are brought in the techniques that are used to isolate the devices in the wafer.
This post describes the silicon-gate process. The important distinguishing characteristics of such structure will be described later.
The fabrication sequence of n-channel MOS IC is shown in the figure below.
Nmos Ic Fabrication Techniques
Nmos IC Fabrication Process

4.NMOS Fabrication Steps

  1. By the process of Chemical Vapour Deposition (CVD), a thin layer of Si3N4 is deposited on the entire wafer surface. With the first photolithographic step, the areas where the transistors are to be fabricated are clearly defined. Through chemical etching, Si3N4 is removed outside the transistor areas. In order to suppress the unwanted conduction between transistor sites, an impurity such as Boron is implanted in the exposed regions. Next, SiO2 layer of about 1 micro meters thickness is grown in these inactive, or field regions by exposing the wafer to oxygen in an electric furnace. This is known as selective or local oxidation process. The Si3N4 is impervious to oxygen and thus inhibits growth of the thick oxide in the transistor regions.
  2. Next, the Si3N4 is removed by an etchant that does not attack SiO2. A layer of oxide about 0.1 micro meters thick is grown in the transistor areas. Then a layer of poly-Silicon is grown over the entire wafer by CVD process. The second photolithographic step shows the desired patterns for gate electrodes. The unwanted poly-Silicon is removed by chemical or plasma etching. In order to introduce a source and drain in particular regions for the MOS device, an n-type dopant, such as phosphorus or arsenic, is introduced. This is done by either Diffusion or Ion Implantation method. The thick field oxide and the poly- silicon gate are barriers to the dopant, but in this process, the poly-Si becomes heavily n-type.
  3. Again, through CVD process, an insulating layer, SiO2, is deposited. As shown in the figure above, the third photolithographic step shows the areas in which contacts to the transistors are to be made. Chemical or plasma etching selectively exposes bare silicon or poly-Si in the contact areas.
  4. Al is used for the interconnection. As shown in the figure above, the fourth masking step shows the Al as desired for the circuit connections.
The final steps of the process are identical to those described for bipolar transistor ICs. Above process is the simplest possible. For advanced processing of NMOS and CMOS, 7 to 12 masking steps are required.

5.PMOS vs NMOS

The advantages of n-channel MOSFET’s over p-channel MOSFET’s and vice versa have been explained in detail. Even the problems that NMOS faces in device processing and oxidation have also been explained.
n-channel MOSFETs have some inherent performance advantages over p-channel MOSFET’s. The mobility of electrons, which are carriers in the case of an n-channel device, is about two times greater than that of holes, which are the carriers in the p-channel device. Thus an n-channel device is faster than a p-channel device. However, PMOS circuits have following advantages
  • PMOS technology is highly controllable.
  • It is a low cost process.
  • It has good yield and high noise immunity.
In addition to inherent fast speed properly, NMOS device also have following advantages.
  • Since electron mobility is twice (say) that of hole mobility, an n-channel device will have one-half the on-resistance or impedance of an equivalent p-channel device with the same geometry and under the same operating conditions. Thus n-channel transistors need only halt the size of p-channel devices to achieve the same impedance. Therefore, n-channel ICs can be smaller for the same complexity or, even more important, they can be more complex with no increase in silicon area.
  • NMOS circuits offer a speed advantage over PMOS due to smaller junction areas. Since the operating speed of an MOS IC is largely limited by internal RC time constants and capacitance of diode is directly proportional to its size, an n-channel junction can have smaller capacitance. This, in turn, improves its speed.

Problems of NMOS

  1. The n-channel device has following problems in the device processing. Most of the mobile contaminants are positively charged. Since NMOS operates with the gate positively based with respect to the substrate, these ions collect along the oxide-silicon interface. This charge causes a shift in VTh. Also, there is fixed positive charge at the Si-SiO2 interface resulting from various steps of the manufacturing process. This also shifts the threshold voltage. Both these charges have tendency to make the device normally on. These two charges exist in PMOS device too, but the positive ions are pulled to the AI-S1O2 interlace by the negative bias applied to gate. There, they cannot affect the device threshold severely.
  2. Another problem with NMOS device occurs during the oxidation of silicon which takes place at the Si-SiO2 interface. No real abrupt change occurs between silicon and Si02; rather there is a transition zone. This transition zone contains positively charged Silicon atoms which increase the absolute magnitude of the threshold voltage for a p-channel device and decrease the absolute magnitude of the threshold voltage for an n-channel device. This means it is difficult to make an n-channel device that is off at zero gate voltage. This is why it is more difficult to make an n-channel device than a p-channel device.

  3. 6.MOSFET Technology

  4. MOSFET Technology and Various MOS Process

    This article focuses on basics of MOSFET Technology,basics of various MOS process like p-channel MOS (PMOS), n-channel MOS (NMOS), Complimentary MOS (CMOS) – its manufacturing, cross section, and other advantages of one over other.
    Most of the LSI/VLSI digital memory and microprocessor circuits is based on the MOS Technology. More transistor and circuit functions can be achieved on a single chip with MOS technology, which is the considerable advantage of the same over bipolar circuits. Below given are the reasons for this advantage of MOS technology:
    • Less chip area is demanded by an Individual MOS transistor, which results in more functions in less area.
    • Critical defects per unit chip area is low for a MOS transistor because it involves fewer steps in the fabrication of a MOS transistor.
    • Dynamic circuit techniques  are practical in MOS technology, but not in bipolar technology. A dynamic circuit technique involves use of fewer transistors to realise a circuit function.
    So you are already clear that because of above said reasons, its considerably cheap to use MOS technology over Bipolar one.
    Three types of MOS process are PMOS, NMOS and Complimentary MOS. Let’s take a look at brief descriptions below.

    p-Channel MOS or PMOS Technology

    This MOS process operates at a very low data rate say 200Kbps to 1Mbps. PMOS is also considered as the first MOS process which required special supply voltages as -9 volts, -12 volts and so on.

    n-Channel MOS  or NMOS Technology

    We can say this is a second generation MOS process, after PMOS, which has considerable improvement in data rates; say up to 2Mbps and resulted in the construction of LSI circuits of a single standard +5volt supply.NMOS increases circuits speed in sharp, because of reduction in the internal dimensions of devices; which is contrary to (and an advantage over) bipolar circuits whose speed increases gradually.The difference in performance between both circuits have steadily become smaller for both LSI and VLSI because of steady improvements in pattern definition capability.
    Have you ever heard of Self aligned silicon gate NMOS ? It’s a commonly used and popular version of MOS technology. Now a days, a technique named as local oxidation is used for this process to improve circuit density and performance. HMOS, SMOS and XMOS are the commonly used names by manufacturers for this. Older versions of the process like Metal Gate NMOS and PMOS are not used now a days for latest designs. A second layer of poly-silicon may be added to the process for important memory applications.

    Complementary MOS Technology

    So you might have already got an idea from the name “Complimentary MOS” ? Its a combination of both n-channel and p-channel devices in one chip. Compared to both other process, CMOS is complex in fabrication and requires larger chip area. Biggest advantage of a CMOS circuit is reduced power consumption (less than NMOS); it is designed for zero power consumption in steady state condition for both logic states. As you may already know, CMOS circuits are widely used in digital equipments like watches, computers etc.
    CMOS offers comparatively higher circuit density and high speed performance (used in VLSI);and this is the primary reason why CMOS is still preferred despite it’s complex manufacturing process. Memories and microprocessors made of CMOS usually employ silicon gate process.
    There are variations of MOS technology which offer either better performance or density advantages over the standard process. Some of those are named as VMOS (V-groove MOS), DSA (Diffusion Self Aligned), SOS (Silicon on Saphire), D-MOS (Double diffused MOS) etc.

    Simple MOSFET Structures

    MOS Technology comprises of 3 process basically, p-channel MOS, n-channel MOS and CMOS process. The basic purpose of all these process is to enhance MOSFET performance one over the other, like lower power consumption, high power capability, relaibility improvements, response speed etc.

    PMOS Structure

    The PMOS is the first device made in metal gate p-channel technology. PMOS infact is an older version of the MOS process which is not used nowadays. A cross sectional view of the PMOS structure is shown below.
    PMOS and NMOS Structures
    PMOS and NMOS Structures
    The starting material is a single crystal Si that is doped n-type with phosphorus or antimony with a doping level on the order of 1015 atoms/cm3.
    So the process is like this, first grow a relatively thick oxide layer; say 1.5micros and then etch windows for the source to drain diffusion. As a next step we have to boron dope the source and drain regions with 2 to 4 micro meters depth. Lets next form the gate oxide, that serves as the dielectric used for turning ON and OFF the MPS device. The entire circuit is then metalised and etched so that there is metal over the gate, drain, and the source. The metal layer should be 1 to 2 micrometers thick and is deposited using an electron beam evaporator.

    NMOS Structure:

    An NMOS structure also follows a similar pattern or sequence as shown in the crosssectional figure above; and is similar to PMOS except for the n+ regions which are diffused into the p-type silicon substrate.

  5. 7.Dielectric Isolation

  6. Dielectric Isolation in Integrated Circuits

    This article focuses on Dielectric isolation in various Integrated Circuits; especially in the VLSI sector, discusses various methods used for dielectric isolation like V-groove isolation, Silicon on Insulator technology and Epitaxial layer overgrowth.
    Dielectric isolation, as you all know, is the process of electrically isolating various components in the IC chip from the substrate and from each other by an insulating layer. It’s main use is to eliminate undesirable parasitic junction capacitance or leakage currents associated with certain applications.
    The various methods of dielectric isolation are:

    V-Groove Isolation

    V-groove isolation is formed with an n-type substrate, on which an n+ diffusion is performed. As a next step an SiO2 layer is formed, which is then patterned to form a grid of intersecting lines opening in the oxide. V-groove isolation process is shown in the figure below.
    V-Groove Dielectric Isolation
    V-Groove Dielectric Isolation
    The wafer formed is then exposed to an orientation dependent etching (ODE) process, where the patterned layer is used as the etching mask; which results in the formation of V-shaped grooves as shown in the picture (b). In this the <111> plane sidewalls are at an angle of 54.74 degree with respect to the <100> top surface of the silicon wafer.
    As a result the starting material is <111> oriented crystal, which is normally used for p-n junction isolation. But for dielectric isolation the starting material is <100> oriental silicon.The etchant used in the above step etches away the exposed silicon anisotropically, this means that the etch rate is much faster along the <111> planes than along the <100> crystal planes. This kind of preferential etching is the key reason behind the formation of V-groove. The depth D of the isolation groove can be determined in the initial oxide cut width Was

    D = W/√2

    Next step is covering the sidewalls of the V-groove with an oxide layer, therefore the wafer is subjected to a thermal oxidation process. After completing the oxide layer, a very thick layer of polycrystalline silicon is deposited as shown in picture (c).
    The most critical step in the V-groove isolation process is explained in figure (d). Keeping polycrystalline surface side of the wafer down, silicon wafers are mounted on the lapping plate. In the next step, n-type silicon substrate is then carefully lapped down to the level at which the vertices of the V-grooves become exposed.So now we get an array of n-type single crystal silicon regions that are isolated from the polycrystalline silicon substrate. Polycrystalline silicon now serves to provide the mechanical support for the IC.This material is ideal for the function because of its good thermal expansion coefficient, it can withstand high processing temperatures, and is a good match to single crystal silicon.
    The n-type silicon has now moved down to vertices of the V-grooves because of the lapping operation. If the lapping is recessive, then proper isolation will not be achieved.But if excessive lapping is done, it may lead to thinner n-type regions. Wafer diameter is approx 100mm and the V-groove depth is about 10 micro meters, thus precise lapping is necessary.
    The n+ diffused layer serves as a buried layer to reduce the collector series resistance of the n-p-n transistors The rest of the processing sequence for the dialectically isolated ICs follows along the same line as for the conventional junction isolated IC.
    The dielectric isolation is useful for such applications as high-voltage and radiation-resistant ICs. This isolation technique is much more expensive than junction isolation technique because it requires extra processing steps.

    Advantage of dielectric isolation:

    Excess free electrons and holes created in the silicon as a result of high energy ionisation by photo radiation causes a large increase in the leakage current of the pn junctions in the IC; which obviously is undesirable and can cause damage.The dielectric isolation in the IC is resistant and protects the IC from such large transients.
    Below listed are some reasons for the reduced parasitic capacitance:
    • Permittivity of SiO2 is one reason, which is 1/3rd of Silicon and hence capacitance is reduced.
    • Oxide is thicker than the depletion region of the substrate junction and capacitance is inversely proportional to the thickness of oxide.
    • No need of applying negetive potential to the substrate.

    Silicon-on-lnsulator Technology

    It’s another process for creating dielectrically isolated devices. In this process, a thin layer of single-crystal silicon can be produced on top of a thermal SiO2 layer on a silicon wafer. Strips of oxide are produced by patterning the oxide layer using photolithography. As a next step, a thin layer of silicon is then deposited on the wafer.It will be polycrystalline in the regions where the deposited silicon layer overlays the oxide and it will be single crystal in the regions where there is direct contact with silicon substrate.  In the next step we will directionally recrystalise the silicon layer, which inturn recrystallises the substrate to act as the nucleation centre.As the heated zone is scanned across the wafer the crystal growth, propagates from these nucleation regions to the regions of the silicon film on top of the oxide islands or strips.Thus we form a complete single crystal layer of silicon.

    Epitaxial Lateral Overgrowth (ELO)

    The Epitaxial Lateral Overgrowth (ELO) is related to Silicon on Insulator process.Like in SOI process, the starting material is thermally oxidised silicon wafer in which the oxide layer is patterned to islands or stripes using photolithographic techniques.Next step is a repeated sequence of carefully controlled CVD silicon deposition, followed vapour phase etching cycles to produce single crystal silicon film on the silicon substrate.
    A preferential removal of polycrystalline silicon (deposited on top of SiO2) happens during the vapour phase etching process.In the next steps,as successive cycles of the CVD deposition and vapour-phase etching process continues,the single-crystal silicon that is formed in the oxide windows starts to extend over the adjoining oxide regions,and at the same time any polycrystalline silicon that is deposited on top of the oxide is removed by the vapour-phase etching process.As a result a complete single crystal layer of silicon is formed.

  7. 8.Monolithic Junction FET’s

  8. The figure below shows some IC JFET structures. The n-channel JFET structure of first figure [a] is compatible with the n-p-n transistor fabrication sequence. Another view of this n-channel JFET is shown in second figure [a], where we note that the top p+ gate region extends beyond the n-type epitaxial layer region to make contact with the p-type substrate bottom gate. The n-type channel is thus completely encircled by the gate structure and the application of a suitably large negative voltage to the gate can pinch the channel off and reduce the drain-to-source current to essentially zero. If the p+ top gate did not extend out to overlap the p-type substrate, the n-type channel would not be completely encircled by the gate structure and it would not be possible to cut off the drain-to-source current. The major drawback or the JFET structure of second figure [a] is that the gate is connected to the p-type substrate, which is at a ground potential. This restricts the use of this structure to only the common-gate configuration.
    Monolithic JFET Structure
    Monolithic JFET Structure
    Second figure [b] shows another n-channel JFET. Its fabrication is similar to the one just considered, the principal difference being in the top surface geometry. In this JFET the p+ top gate is in the form of an annual ring that completely encloses the drain region of the JFET. The only current path from source to drain will be underneath the p+ top gate. Therefore the application of a suitably large negative voltage to the top gate can pinch off the channel and reduce the drain-to-source current to essentially zero.
    First figure [b] shows a p-channel JFET. The n+ gate region of this device extends out beyond the source/drain/channel region to overlap the n-type epitaxial layer so that the gate completely encircles the channel. The same processing sequence can be used for this JFET as for the n-p-n transistor. But, if this is done, the gate-to-channel breakdown voltage (corresponding to BVtRo) will be down in the range 6 to 8V and the full pinch-off of the channel may not be possible. As a result, a specially tailored low-concentration boron diffusion will be required to produce a higher gate –channel breakdown voltage and lower channel doping; so that the channel can be pinched off at a voltage that is conveniently less than the breakdown voltage. This, however, requires some extra processing steps making the device more expensive.
    Monolithic n-channel JFET
    Monolithic n-channel JFET
    A p-channel JFET employing boron- lon-implanted channel is shown in first figure [c]. Since the ion implantation dosage can be very precisely controlled, the JFET parameters, such as Vp and IDss can be closely set to the values desired This JFET uses the same processing steps as the n-p-n transistor, with the addition of a photolithography, boron ion implantation and annealing step.

  9. 9.Monolithic Diodes

  10. Monolithic Planar Diode Configurations

    We have seen that in the fabrication of an IC the geometry and the doping of the various layers must be chosen to optimize uncharacteristic of the transistor which is the most important device. It is not economically feasible to provide extra processing steps to fabricate diodes. Therefore diodes are generally transistor adopted for this operation. There are basic five configurations of transistor for diode operation as shown in the figure below.
    A base-collector diode is shown in figure [a]. The emitter is floating and can be omitted. This diode has a high breakdown voltage  of around 50 V. However it has a relatively long switching time of about 100 nano seconds due to the collector access resistance Rcc, which is nothing but the resistance between the collector terminal and the effective active region to which it is connected. (This resistance is reduced by buried layer diffusion).
    The switching time can be improved to about 70 nano seconds by shorting the emitter and base to remove charge stored at that junction, while retaining the high breakdown voltage, as shown in figure [b].
    Figure [c] shows the base-emitter junction diode with collector open. The turn-off time, due mainly to charge stored in the base collector junction is about 80 nano seconds and it has a low breakdown voltage (associated with the high doped emitter of around 5V.
    In above case, the switching time can be reduced to as low as 20 nano seconds, by shorting base and collector, to remove minority stored charge as shown in figure [d]. The low breakdown voltage is not affected in this diode.
    Figure [e] shows the diode connection where both emitter-base and base-collector junctions are in parallel. It is obtained by shorting emitter and collector. This diode is not much used due to high junction capacitance which causes low switching speed of around 150 nano seconds, together with a poor breakdown voltage of about 5V associated with the base-emitter junction.
    Various Diode Configurations
    Various Diode Configurations
    From above discussion we conclude that diodes shown in figure [b] and [d] are most useful, the former for higher voltage applications, and the latter where switching speed is of paramount importance. Supply voltage encountered and digital ICs rarely exceed 5 or 6 V, hence the limitation of low breakdown voltage of diodes shown in figure [d] is not a serious disadvantage. Further it has the lowest series resistance and no parasitic p-n-p action to the substrate (which occurs between the substrate and the p-type base, if the collector-base region of the n-p-n were to become forward biased). Also it has generally the lowest forward voltage drop for a given forward current, lowest storage time and lowest reverse-bias capacitance. These all favourable factors make the diode of figure [d] an ideal choice for digital IC’s.

    Avalanche Diode

    The avalanche breakdown characteristic in a reverse biased diode can be used for voltage reference or the dc level-shift purposes in IC circuits. The base-emitter breakdown voltage which falls within the 6 to 9 V range is the most commonly used avalanche diode since its breakdown voltage incompatible with the voltage levels available in analog circuits.
    The breakdown voltage of base-emitter junction of above diode exhibits a positive temperature coefficient, typically in the range of +2 mV/°C to +5 /°C. By connecting a forward-biased diode in series with avalanche diode, it is possible to partially compensate the thermal drift of avalanche diode because the thermal drift of forward voltage of the series connected diode is negative. The composite connection is shown in the figure below which has breakdown voltage of (VD + BVEB) with significantly reduced temperature coefficient. Here VD is forward drop of series diode and BVEB is the breakdown voltage (BE junction) of avalanche diode. As the figure shows, the composite connection consists of two transistors back-to-back in diode connection. Since both transistors have their collector and base regions in common, they can be designed as a single transistor with two separate emitters.
    Avalanche Diode
    Avalanche Diode

    Schottky Diode and Transistor

    When a metal is placed in close contact with an n-type semiconductor, a voltage barrier is created, which is known as Schottky Barrier. ln such contact,  there are many free electrons in the metal, whereas the semiconductor contains relatively low. With a positive voltage applied to the metal, the barrier is overcome and the diode begins conducting. A negative bias enlarges the barrier, thus the diode blocks conduction. Such diode differs from an ordinary p-n junction as follows:
    The barrier is only half as large as that of a junction diode, at low current, a Schottky diode has a forward voltage drop of only about 0.3 V to 0.5 V.
    Only majority carriers are involved in the conduction mechanism, which make the Schottky diode a very high speed device with a recovery time less than 1 nano seconds.
    The Schottky effect only takes place in relatively high resistivity semiconductor material. When the semiconductor is heavily doped, a tunnelling effect occurs which provides a direct ohmic contact.
    The figure below shows the cross-section view of a typical Schottky diode. It is formed between the epitaxial layer and the Al deposited for interconnections. The cathode connection to the epitaxial layer is through a conventional n+ collector contact diffusion, to ensure a good ohmic contact, but at the anode connection the n+ diffusion is omitted due to direct ohmic contact provided by Schottky junction. The Schottky barrier is formed between aluminium and the n-type epitaxial silicon. The advantage of Schottky diode is that it can be made with existing IC processes. No additional manufacturing steps are required. This is important from yield point of view.
    Schottky Diode
    Schottky Diode
    One important application of Schottky diode is Schottky diode clamped transistor is shown in the figure below. The figure [a] shows circuit symbol and [b] shows the cross-sectional view of Schottky transistor. The Schottky transistor is used in TTL logic circuits. The Schottky transistor provides very fast speed operation. This is possible because the Schottky clamp prevents the transistor from going into saturation. If an attempt is made to saturate this transistor by increasing the base current, the collector voltage drops, diode D conducts, and the base-to-collector voltage is limited to about less than 0.5. V. Since the collector junction is forward-biased by less than the cut-in voltage (0.5 V), the transistor does not enter saturation.
    Schottky Transistor
    Schottky Transistor
    Note that in the figure [b], the aluminium metallization for base lead is allowed to make contact also with the n-type collector region, but without an intervening n+ layer. This results in formation of metal semiconductor diode between base and collector. Since the Schottky junction is formed during the metallization process, the Schottky transistor requires the same number of process steps as does an n-p-n transistor.
    For practical Schottky diodes, the dominant reverse current component is the edge leakage current which is caused by the sharp edge around the periphery of the metal plate. To eliminate this effect metal semiconductor diodes are fabricated with a diffused guard ring as shown in the figure [b]. The guard ring is deep p-type diffusion and the doping profile is tailored to give the p-n junction a higher breakdown voltage than the metal semiconductor contact, thus preventing premature breakdown and surface leakage.

10.P-N Junction Isolation

Once all components are fabricated on a single crystal wafer, they must be electrically isolated from each other. The problem is not encountered indiscrete circuits, because physically all components are isolated. There are two methods of isolation in Integrated circuits. They are
  • P-N  junction isolation and
  • Dielectric isolation
In this post we shall discuss p-n junction isolation.
The method of isolation is most compatible with the IC processing, that is, one extra processing step, other than required to fabricate IC, is required in isolation. Basically the method involves producing islands of n- type material surrounded by p-type material. Components are then fabricated in different n-type islands. The p-type material surrounding the islands is given the most negative p potential with respect to all parts of the wafer, thus each island and hence component is electrically isolated from the others by back-to-back diodes. The process step for p-n junction isolation are explained below:
1. One begins with the p-type substrate on which n-epitaxial layer is grown. If the component to be fabricated is transistor, then buried layer have to be formed before growing epi-layer. Figure [a] shows epi-layer growth over substrate without buried layer. The epi-layer is then covered with SiO2 layer.
2. A p-type diffusion is now performed from the surface of the wafer. Since this is to be performed in selected areas, an isolation mask is prepared prior to this diffusion. A long drive-in time is required for p-type diffusion so that the acceptor concentration is greater than the epi-layer donor concentration throughout the region of epi-layer. Thus the portion of wafer at the location of isolation diffusion is changed to p-type from the surface of wafer to the substrate. This is shown in the figure [b]. In other words, the substrate is extended toward the surface and acts as an isolation wall. This isolation wall causes the formation of p-n junction everywhere around the n-type islands except at the surface. If the substrate is connected to a voltage which is more negative than any of the n-region voltages, the diodes shown will be reversed biased and negligible current will flow. Thus isolation is achieved since any reverse biased p-n junction is associated with a depletion capacitance; this will have parasitic effect associated with junction, particularly, at high frequencies.
P-N Junction Isolation
P-N Junction Isolation
The main disadvantage of p-n junction isolations is as below:
  1. The time required for such isolation technique is considerably longer due to diffusion time taken, which is longer than any of other diffusions.
  2. Lateral diffusion is significant due to longer time taken by isolation diffusion, hence considerable clearance must be used for isolation regions.
  3. Isolation diffusion takes an area of the wafer surface which is significant portion of the chip area. From component density consideration, this area is wasted.
  4. P-N junction isolation method introduces significant parasitic capacitance which degrades circuit performance. The parasitic capacitance is introduced by isolation sidewall and bottom epitaxial substrate junction.
Several methods have been developed by manufacturers to avoid above problems. All of these methods circumvent the problems of large area and sidewall capacitance, but they suffer from the parasitic capacitance introduced by bottom epi-substrate junction. Dielectric isolation avoids this problem too.


No comments:

Post a Comment

Subscribe to: Post Comments (Atom)